For a clock signal combined or synthesized from multiple-phase signals, as there are mismatches among different input phase paths, the synthesized clock signal may have spurs or jitters.
A conventional solution to reduce or eliminate mismatch is to decompose the synthesized clock signal by a frequency divider, to output new plurality of phase shifted signals, and test the duty cycle of each of the plurality of phase shifted signals, therefore adjusting mismatch of the input signals. However, such method will introduce additional mismatch, such as an offset of comparator or resolution of analog-digital converter (ADC) used to detect clock's mismatch.